It is known in the prior art that integrated circuits containing tens of thousands of transistors on a single semiconductive substrate or chip may be fabricated and that such transistors must be electrically interconnected to form desired circuits. A semiconductor chip typically measures about one-quarter of an inch on a side, or less. For any desired integrated circuit function, the chip area is determined primarily by the area devoted to the isolation between devices; the devices (transistors, capacitors, resistors), the interconnection lines (diffused silicon, polysilicon, aluminum), and the intraconnection contacts or vias that electrically connect one conductive line type to another. One of the elements of a conventional integrated circuit which has large area requirements is the metal-to-diffused silicon or metal-to-implanted silicon contact.
Methods for providing intraconnection contact holes or "vias" are known in the art. FIG. 1 illustrates a conventional contact via formed by chemical or plasma etching through a thermally grown or chemically vapor deposited (CVD) oxide. Although the situation of perfect mask-to-mask alignment is illustrated, a misalignment region or border 1 must be provided between the boundary 2 of the contact via and the boundary 3 of the recessed isolation oxide. FIG. 2 shows the etched contact via method of FIG. 1, but in the case of a significant mask-to-mask misregistration. In forming the contact via by etching, over-etching is required to insure that all of the oxide is removed from all of the contact vias on the chip. If, due to mask-to-mask misregistration, the contact via is partially located over the recessed isolation oxide, some of the recessed oxide will be removed during the over-etching step as shown in FIG. 2. The metal interconnection material, aluminum, for example, may then electrically short to the p-type substrate rendering the circuit inoperable. The shorting problem just described is accentuated when very shallow (less than 0.5 micron) n-type source and drain regions are used in very large scale integrated (VLSI) FET circuits. One prior art approach for eliminating the above described shorting problem is shown in FIG. 3. FIG. 3 is a cross-sectional drawing of an etched, non self-aligned via connection in which the contact area has been rediffused with a fast diffusing species such as phosphorus. In FIG. 3, a contact hole is opened by conventional etching through an oxide layer over a shallow arsenic doped n-type region 4. Then, a thin layer of phosphorus-rich glass is deposited over the entire substrate, and phosphorus is diffused into the contact hole. Phosphorus diffuses much faster than arsenic and thus a deeper n-type diffused region 5 is formed in the vicinity of the contact hole. Now, an additional masking step is used to reopen the contact holes through the thin phosphorus doped glass layer and a metal contact is formed as shown in FIG. 3. Thus, the electrical shorting problem shown in FIG. 2 is eliminated but at the expense of an additional deposition step and an additional masking operation.
Other difficulties associated with etched contact vias to diffused regions involve the contact resistance, pinhole reliability, and metal step coverage.
FIG. 4 illustrates a difficulty that occurs if one attempts to locate a minimum allowable size contact hole (typically about 2.5 microns in diameter) on a minimum width diffused line (typically about 2.5 microns wide). The contact resistance is inversely proportional to the area of contact to the n-type region. If, for example, the mask-to-mask misregistration is about 1.25 microns as shown in FIG. 4, the contact resistance will be about double that of the perfectly registered case. Such fluctuations in contact resistance are generally intolerable, and in order to prevent them, the doped n-type region typically is expanded in the vicinity of a contact via, as shown in FIG. 1, to eliminate or at least minimize contact resistance variations. Another difficulty is associated with etching contact vias through thick oxide layers. During etching of the intended contact via, any defect in the masking pattern or in the resist layer will provide a site for etching an unwanted via, or pinhole. Wherever a metal interconnection line crosses a pinhole, an unwanted electrical short circuit to a device region or to the substrate may occur. In order to reduce the detrimental occurrence of contact via pinholes, double masking and/or double etching operations can be utilized, but with a resultant increase in fabrication complexity and cost.
Yet another difficulty associated with etched contact vias is the metal step coverage or thinning at the boundary of the via as shown at 6 in FIG. 4. This problem has been described, for example, by R. A. Moline, R. R. Buckley, S. E. Hoszko, and A. U. MacRae, "Tapered Windows in SiO.sub.2 by Ion Implantation", IEEE Trans. Electron Dev., ED-20, p. 840, Sept. (1973). These authors describe the use of ion implantation to locally alter the etching rate of the insulating oxide layer, thereby reducing the severity of the step.
Apart from the above-described considerations, some of the individual steps or combinations of steps utilized in the practice of the present invention are known. For example, the formation of selective, local or semi-recessed oxide isolation regions is described in U.S. Pat. No. 3,751,722, filed Apr. 30, 1971, and U.S. Pat. No. 3,752,711, filed June 1, 1971. A method for forming fully-recessed oxide isolation regions is described in U.S. Pat. No. 3,899,363, filed June 28, 1976 and assigned to the same assignee as the present invention. These patents utilized a delineated oxidation barrier layer such as silicon nitride, aluminum nitride, boron nitride, aluminum oxide, or silicon carbide to permit recessed oxide isolation regions to be thermally grown everywhere in the surface of a silicon substrate except where surface is masked by portions of the delineated oxidation barrier layer. After thermal growth of the recessed isolation oxide, all the methods of the above-mentioned patents utilized a step which completely removes the remaining portions of the oxidation barrier layer by dissolving them in a suitable etchant. In contrast to this, the method of the present application patterns by masking, and removes by etching, only a portion of the remaining oxidation barrier layer so that self-aligned contact areas can be formed.
In the prior art, the region where the oxidation barrier is removed is subjected to an etch and subsequent growth of a recessed isolation oxide. In yet another prior art approach, in U.S. Pat. No. 3,834,959, filed June 30, 1972 and assigned to the same assignee as the present invention, an oxidation barrier such as silicon nitride is deposited and delineated in certain places and subsequently remains in place as an oxidation barrier during later processing. It is never subsequently removed nor is any portion of it removed and it appears as a gate dielectric in the resulting structure. In contrast, in the present method, the nitride is patterned twice; first, to define the recessed oxide isolation regions and what remains is etched a second time to reduce the size of the oxidation barrier to contact size proportions. An insulation oxide regrowth step now forms a thick insulation oxide which extends to the new boundary of the oxidation barrier layer such that the latter is surrounded by recessed oxide and thick insulation oxide. Removal by dissolving of the remaining portion of the oxidation barrier layer now provides a contact via self-aligned to an underlying doped region which was formed by ion implantation or diffusion prior to the insulation oxide regrowth.
Accordingly, it is an object of the present invention to provide an improved method for fabricating intraconnection contact vias between metal interconnection lines and doped regions of a semiconductive substrate for electrically interconnecting transistors and other devices of an integrated circuit.
A further object of the invention is to provide a method for fabricating contact vias in which at least a portion of the boundary of the via is self-aligned to the boundary of the recessed isolation oxide and/or to the boundary of the underlying doped semiconductor region, and, wherein the underlying doped areas are greater in area than the desired contact areas.
Another object of the invention is to provide a method for fabricating a contact via of minimum size on a doped line of minimum width without significant fluctuations in contact area or in contact resistance.
Still another object of the invention is to avoid etching contact vias through a thick oxide layer thereby avoiding potential pinhole reliability problems.
Still another object of the present invention is to provide metal to doped region contact vias with improved metal coverage of the oxide step at the boundary of the contact via.